Memory device power distribution in memory assemblies

ABSTRACT

A memory assembly has a memory package with a plurality of interconnect pins having a plurality of first power input pins located on a first side of the memory package, the first power input pins independent of each other. A lead-over-chip leadframe has a plurality of leads coupled to the plurality of interconnect pins in a one-to-one relationship. A memory chip is coupled to the plurality of leads and has substrate with a memory device fabricated thereon and a plurality of first power input chip bond pads fabricated thereon and coupled to the memory device. Each first power input chip bond pad is further coupled to one of the first power input pins through one of the leads.

RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.10/348,537 (pending), filed Jan. 21, 2003 and titled, “MEMORY DEVICEPOWER DISTRIBUTION IN MEMORY ASSEMBLIES,” which is commonly assigned andincorporated by reference in its entirety herein and which is adivisional of U.S. patent application Ser. No. 09/648,880, filed Aug.25, 2000, titled, “MEMORY DEVICE POWER DISTRIBUTION,” and issued as U.S.Pat. No. 6,541,849 on Apr. 1, 2003.

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to semiconductor memory devices,and in particular, the present invention relates to power distributionfor semiconductor memory devices.

BACKGROUND OF THE INVENTION

Memory devices are typically provided as internal storage areas in thecomputer. The term memory identifies data storage that comes in the formof integrated circuit chips. There are several different types ofmemory. One type is RAM (random-access memory). This is typically usedas main memory in a computer environment. RAM refers to read and writememory; that is, you can repeatedly write data into RAM and read datafrom RAM. This is in contrast to ROM (read-only memory), which generallyonly permits the user in routine operation to read data already storedon the ROM. Most RAM is volatile, which means that it requires a steadyflow of electricity to maintain its contents. As soon as the power isturned off, whatever data was in RAM is lost.

Computers almost always contain a small amount of ROM that holdsinstructions for starting up the computer. Unlike RAM, ROM generallycannot be written to in routine operation. An EEPROM (electricallyerasable programmable read-only memory) is a special type ofnon-volatile ROM that can be erased by exposing it to an electricalcharge. Like other types of ROM, EEPROM is traditionally not as fast asRAM. EEPROM comprise a large number of memory cells having electricallyisolated gates (floating gates). Data is stored in the memory cells inthe form of charge on the floating gates. Charge is transported to orremoved from the floating gates by programming and erase operations,respectively.

Yet another type of non-volatile memory is a Flash memory. A Flashmemory is a type of EEPROM that can be erased and reprogrammed in blocksinstead of one byte at a time. Many modern PCs have their BIOS stored ona flash memory chip so that it can easily be updated if necessary. Sucha BIOS is sometimes called a flash BIOS. Flash memory is also popular inmodems because it enables the modem manufacturer to support newprotocols as they become standardized.

A typical Flash memory comprises a memory array that includes a largenumber of memory cells arranged in row and column fashion. Each of thememory cells includes a floating gate field-effect transistor capable ofholding a charge. The cells are usually grouped into blocks. Each of thecells within a block can be electrically programmed in a random basis bycharging the floating gate. The charge can be removed from the floatinggate by a block erase operation. The data in a cell is determined by thepresence or absence of the charge in the floating gate.

A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higherclock speeds than conventional DRAM memory. SDRAM synchronizes itselfwith a CPU's bus and is capable of running at 100 MHZ, about three timesfaster than conventional FPM (Fast Page Mode) RAM, and about twice asfast EDO (Extended Data Output) DRAM and BEDO (Burst Extended DataOutput) DRAM. SDRAMs can be accessed quickly, but are volatile. Manycomputer systems are designed to operate using SDRAM, but would benefitfrom non-volatile memory.

Many SDRAM devices are housed in packages that have an industry-standardpin layout and are of specified lengths and widths, such as a TSOP(thin, small-outline package) having a width of about 400 mils and alength dependent upon the number of pins. Memory chips in known TSOPmemory packages have been oriented lengthwise within the package, asillustrated in FIG. 1A, and orthogonally within the package, asillustrated in FIG. 1B. FIGS. 1A and 1B depict industry-standard pinlayouts for 44-pin SDRAM TSOP packages.

In the assembly depicted in FIG. 1A, memory chip 60 is orientedlengthwise within the package 62 with the major axis of the memory chip60 extending substantially parallel to the major axis of the package 62.In the memory chip 60 of FIG. 1A, chip bond pads are located at oppositeends of the memory chip 60.

In the assembly depicted in FIG. 1B, memory chip 60 is orientedorthogonally within the package 62 with the major axis of the memorychip 60 extending substantially perpendicular to the major axis of thepackage 62. In the memory chip 60 of FIG. 1B, chip bond pads are locatedbetween the banks of memory arrays, or memory banks 64, located onmemory chip 60.

For either assembly type, the chip bond pads correspond to interconnectpins of the package 62, such as address pins, data pins, clock andcontrol signal pins, and power input pins. In general, there is aone-to-one relationship between the chip bond pads of a memory chip 60and the interconnect pins of a package 62. However, certain interconnectpins may couple to more than one chip bond pad. The chip bond pads ofthe memory chip 60 are coupled to the interconnect pins of the package62 in a conventional manner.

Integrated circuit chips, such as memory chips 60, are generally poweredusing a supply potential, such as VCC, and a ground potential, such asVSS. The industry-standard pin layouts for current SDRAM packagesrequire power input pins for the ground potential VSS on a first side 74of the package 62 and power input pins for the supply potential VCC on asecond and opposite side 76 of the package 62. VCC power chip bond pads66 are generally located on opposing ends of the memory chip 60 and arecoupled to the VCC power input pins located near their correspondingend. For example, VCC power chip bond pads 66 located adjacent end 70 ofthe package 62 are coupled to the VCC power input pin located near end70 while VSS power chip bond pads 68 located adjacent end 72 of thepackage 62 are coupled to the VSS power input pin located near end 72.To simplify the drawings, remaining chip bond pads, such as clock andcontrol signal chip bond pads CLK, CKE, DQM, RAS#, CAS#, WE# and CS#,data chip bond pads DQ0-DQ7, address chip bond pads A0-A10 and BA, andDQ power input chip bond pads VCCQ and VSSQ, are not labeled in FIGS.1A-1B.

As memory devices continue increasing in overall memory size and speed,power distribution becomes more critical especially as design rulescontinue to decrease. However, the industry-standard pin layoutsrestrict the ability of the designer to freely place power chip bondpads 66 and 68 around the memory chip as all VCC power input pins are onone side 76 of the package 62 while all VSS power input pins are on theopposite side 74 of the package 62.

Furthermore, to reduce undesirable parasitics, the VCC power chip bondpads 66 are usually coupled by a power connection internal to the memorychip 60. Likewise, the VSS power chip bond pads 68 are usually coupledby a second power connection internal to the memory chip 60. These powerconnections may take the form of a semiconductor die metalization layer.Such power connections use a significant amount of die real estate toconnect these sources together properly, thus increasing costs andreducing production capacity. Furthermore, if the IR(inductance/resistance) drop along these power connections is too high,voltage drops or fluctuations may create undesirable signalcharacteristics within the integrated circuit. These concerns aremagnified for those architectures having the memory device locatedbetween the power chip bond pads.

For the reasons stated above, and for other reasons stated below whichwill become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art foralternate architecture and assembly of semiconductor memory devices.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic of one known memory assembly having a lengthwiseorientation.

FIG. 1B is a schematic of another known memory assembly having anorthogonal orientation.

FIG. 2 is a block diagram of a memory device in accordance with theinvention.

FIG. 3 is a top view of a memory assembly showing a package pininterconnect diagram in accordance with the invention.

FIG. 4 is a schematic of a memory chip in accordance with the invention.

FIG. 5 is an assembly detail drawing of a lead-over-chip leadframeattached to a memory chip in accordance with the invention.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description of the present embodiments,reference is made to the accompanying drawings that form a part hereof,and in which is shown by way of illustration specific embodiments inwhich the inventions may be practiced. These embodiments are describedin sufficient detail to enable those skilled in the art to practice theinvention, and it is to be understood that other embodiments may beutilized and that process, electrical or mechanical changes may be madewithout departing from the scope of the present invention. The termswafer or substrate used in the following description include any basesemiconductor structure. Both are to be understood as includingsilicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI)technology, thin film transistor (TFT) technology, doped and undopedsemiconductors, epitaxial layers of a silicon supported by a basesemiconductor structure, as well as other semiconductor structures wellknown to one skilled in the art. Furthermore, when reference is made toa wafer or substrate in the following description, previous processsteps may have been utilized to form regions/junctions in the basesemiconductor structure, and terms wafer or substrate include theunderlying layers containing such regions/junctions. The followingdetailed description is, therefore, not to be taken in a limiting sense,and the scope of the present invention is defined only by the appendedclaims and equivalents thereof.

Referring to FIG. 2, a block diagram of one embodiment of the presentinvention is described. The memory device 100 includes an array ofnon-volatile flash memory cells 102. All access commands of the memorydevice 100 are synchronized to a system clock input signal (CLK), thusthe memory device 100 may be referred to as a synchronous flash memorydevice. The array is arranged in a plurality of addressable banks. Inone embodiment, the memory contains four memory banks 104, 106, 108 and110. Each memory bank contains addressable sectors of memory cells. Thedata stored in the memory can be accessed using externally providedlocation addresses received by address register 112 through a pluralityof address inputs 138. The externally provided location addresses may beprovided by a processor 101 of an electronic system as is known in theart. The addresses are decoded using row address multiplexer circuitry114. The addresses are also decoded using bank control logic 116 and rowaddress latch and decode circuitry 118. To access an appropriate columnof the memory, column address counter and latch circuitry 120 couplesthe received addresses to column decode circuitry 122. Circuit 124provides input/output (I/O) gating, data mask logic, read data latchcircuitry and write driver circuitry. Data is input through data inputregisters 126 and output through data output registers 128 using aplurality of data inputs/outputs 140, which are generally coupled to theprocessor 101 of an electronic system. Command execution logic 130 isprovided to generate commands to control the basic operations performedon the memory banks of the memory device. A state machine 132 is alsoprovided to control specific operations performed on the memory banks. Astatus register 134 and an identification register 136 can also beprovided to output data. The command circuit 130 and/or state machine132 can be generally referred to as control circuitry to control read,write, erase and other memory operations. As is known in the art,integrated circuit memory devices of the type described with referenceto FIG. 2 may be fabricated on a substrate, such as a semiconductor die,and may be referred to as a memory chip.

FIG. 3 illustrates an interconnect pin assignment of one embodiment ofthe present invention as a memory assembly having a pin layoutsubstantially similar to a standard SDRAM 54-pin TSOP package.Accordingly, the memory assembly has a memory package 150 having 54interconnect pins. The memory package 150 has n interconnect pins oneach side, with n equal to 27 for the embodiment depicted in FIG. 3. Thememory package 150 may have some other number of interconnect pins.

The interconnect pins of a memory package 150 generally number 1 throughn proceeding numerically from the top to the bottom of the memorypackage 150 on side 176 and n+1 through 2n proceeding numerically fromthe bottom to the top of the memory package 150 on side 174. Thus thefirst pin on the top of side 176 is number 1, the center pin on side 176(if n is odd) is number (n+1)/2, the last pin on the bottom of side 176is n, the first pin on the bottom of side 174 is number (n+1), thecenter pin on side 174 (if n is odd) is number (3n+1)/2, and the lastpin on the top of side 174 is number 2n.

The memory package 150 contains a memory chip (not shown in FIG. 3) inaccordance with the invention. As such, the memory package 150 maycontain a synchronous flash memory device. Two interconnects shown inthe embodiment of FIG. 3 and not present in standard SDRAM packagesinclude control signal RP# and power input VCCP. Although knowledge ofthe function of the various clock and control signals and the variouspower inputs is not essential to understanding the present invention, adetailed discussion is included in U.S. patent application Ser. No.09/567,733 filed May 10, 2000 and titled, “Flash with ConsistentLatency,” which is commonly assigned. Furthermore, the invention is notlimited to memory packages having pin layouts substantially similar toan industry-standard SDRAM pin layout, but is applicable to other memorypackages using a leadframe having composite leads for coupling aninterconnect pin to chip bond pads located in multiple quadrants of amemory chip or on opposite sides of the memory chip.

FIG. 4 depicts a simplified schematic of a memory chip 460 having fourmemory banks 464 ₀-464 ₃. While the memory banks 464 have been shown asa substantially contiguous structure, there is no requirement that thememory banks 464 be physically adjoining. However, reducing spacingbetween the memory banks 464 may provide improvements in die efficiency.The various embodiments facilitate reductions in spacing by eliminatingthe need to run a low IR power connection from one side of the memorychip 460 to the other as part of the fabrication process; as describedbelow, a leadframe may be used to couple the power input chip bond padson both sides of the memory chip 460. Memory chip 460 may contain asynchronous flash memory device as described with reference to FIG. 2.Memory chip 460 may alternatively contain other memory devices or othernumbers of memory banks. The memory chip 460 is arranged to be mountedin a memory package with the major axis of the memory chip 460 alignedsubstantially parallel with the major axis of its memory package.

The memory chip 460 has at least two sets of power input chip bond padsfor coupling to the power input pins of a memory package. A first set ofpower input chip bond pads may correspond to the supply potential, orVCC, power input pins of the memory package 150. Such VCC power inputchip bond pads 466 are coupled to the various elements of the memorydevice through a first power bus for the distribution of power withinthe memory chip 460. A second set of power input chip bond pads maycorrespond to the ground potential, or VSS, power input pins of thememory package 150. Such VSS power input chip bond pads 468 are coupledto the various elements of the memory device through a second power busfor the distribution of power within the memory chip 460. The variouschip bond pads are fabricated on the substrate as part of the memorychip 460.

The VCC power input chip bond pads 466 and VSS power input chip bondpads 468 are located adjacent a first side 484 and a second side 486 ofthe memory chip 460 (or substrate). The power input chip bond pads 466and 468 are interposed between the memory banks 464 and the sides 484and 486 of the memory chip 460 (or substrate).

For one embodiment, at least one VCC power input chip bond pad 466 islocated in each of at least three quadrants of the memory chip 460. Asthe quadrants of the memory chip 460 correspond to the quadrants of thesubstrate on which the memory device is fabricated, the terms may beused interchangeably. For the embodiment depicted in FIG. 4, two VCCpower input chip bond pads 466 are located in the first quadrant 452,four VCC power input chip bond pads 466 are located in the thirdquadrant 456, and one VCC power input chip bond pad 466 is located inthe fourth quadrant 458.

For one embodiment, at least one VSS power input chip bond pad 468 islocated in each of at least three quadrants of the memory chip 460. Forthe embodiment depicted in FIG. 4, two VSS power input chip bond pads468 are located in the first quadrant 452, one VSS power input chip bondpad 468 is located in the second quadrant 454, and four VSS power inputchip bond pads 468 are located in the third quadrant 456.

Although not labeled in FIG. 4, remaining chip bond pads include clockand control signal chip bond pads, data chip bond pads, and address chipbond pads. A more detailed discussion of such remaining chip bond padsis included in U.S. patent application Ser. No. 09/642,683 filed Aug.21, 2000 and titled, “Architecture, Package Orientation and Assembly ofMemory Devices,” which is commonly assigned.

The memory chip 460 of FIG. 4 offers certain advantages. By placingpower input chip bond pads around the perimeter of the memory chip 460,power distribution within the memory chip 460 may be improved. Suchplacement of power input chip bond pads can be used to reduce thepotential for hot spots, to reduce the inductance of the powerdistribution buses, and to increase the ability of the integratedcircuit device to handle surges in current.

For one embodiment, at least one power input chip bond pad 466 or 468 islocated near each corner of the memory chip 460. For another embodiment,at least one power input chip bond pad 466 or 468 is further locatednear the center of each side 484 and 486 of the memory chip 460.

To couple the chip bond pads of memory chip 460 to the pins of a memorypackage, an LOC (lead-over-chip) leadframe may be used. LOC leadframesare well known in the art of packaging semiconductor chips. LOCleadframes generally contain a pressure-sensitive adhesive portion forsecuring the chip and a plurality of conductive leads for coupling thechip bond pads to pins of a semiconductor package. As the generalconstruction, alignment and use of such LOC leadframes is well known,the following discussion will be limited to those factors that arepertinent to the various embodiments of the invention.

FIG. 5 is an assembly detail drawing showing attachment of a memory chip460 to an LOC leadframe 590. As shown, the LOC leadframe 590 is adaptedfor coupling chip bond pads of memory chip 460 to the interconnect pinsof memory package 150. Accordingly, the LOC leadframe 590 has leadshaving a one-to-one correspondence to the interconnect pins of memorypackage 150.

A first plurality of leads includes short leads, such as lead 592,extending from side 584 of the LOC leadframe 590 and originating in afirst quadrant 552. Leads 592 correspond to data pins on side 174 of thememory package 150. The term “short” as used herein does not directlyrelate to physical length. As used herein, a lead is short if itterminates between a centerline 591 of the LOC leadframe 590 and theside from which it extends. Stated alternatively, a lead is short if itterminates in the same quadrant from which it originates. A secondplurality of leads includes long leads, such as leads 593, extendingfrom side 586 of the LOC leadframe 590 and originating in a fourthquadrant 558. Leads 593 correspond to data pins on side 176 of thememory package 150. The term “long” as used herein does not directlyrelate to physical length. As used herein, a lead is long if itterminates between the centerline 591 of the LOC leadframe 590 and theside opposite from which it extends. Stated alternatively, a lead islong if it terminates in a quadrant other than the quadrant from whichit originates.

A third plurality of leads includes short leads, such as leads 595,extending from the side 586 of the LOC leadframe 590 and originating inthe third quadrant 556. Leads 595 correspond to address pins on side 176of the memory package 150. A fourth plurality of leads includes longleads, such as leads 596, extending from the side 584 of the LOCleadframe 590 and originating in the second quadrant 554. Leads 596correspond to address pins on side 174 of the memory package 150.

A fifth plurality of leads includes composite leads 594 ₁ and short lead594 ₂ extending from side 584 of the LOC leadframe 590. A lead is acomposite lead, such as leads 594 ₁, if it is a composite of short andlong leads and thus has terminations on each side of the centerline 591or in multiple quadrants. Composite leads, when coupled to chip bondpads of the memory chip 460, effectively short a chip bond pad on oneside of the memory chip 460 to a chip bond pad on the other side of thememory chip 460. The fifth plurality of leads corresponds to VSS powerinput pins on side 174 of the memory package 150. Use of a compositelead permits location of VSS power input chip bond pads 468 in multiplequadrants and on opposite sides of the memory chip 460 for coupling to asingle VSS power input pin of the memory package 150. Accordingly, theplurality of leads corresponding to the VSS power input pins includes atleast one composite lead 594 ₁. For one embodiment, a majority of theleads corresponding to the VSS power input pins are composite leads. Foranother embodiment, each VSS power input pin corresponds to at least twoVSS power input chip bond pads 468. For a further embodiment, the numberof VSS power input chip bond pads 468 is at least two times the numberof VSS power input pins of the memory package. For yet anotherembodiment, the number of VSS power input chip bond pads 468 is equal toor greater than three times the number of VSS power input pins of thememory package.

A sixth plurality of leads includes composite leads 5971 and short lead5972 extending from side 586 of the LOC leadframe 590. The sixthplurality of leads corresponds to VCC power input pins on side 176 ofthe memory package 150. Use of a composite lead permits location of VCCpower input chip bond pads 466 in multiple quadrants and on oppositesides of the memory chip 460 for coupling to a single VCC power inputpin of the memory package 150. Accordingly, the plurality of leadscorresponding to the VCC power input pins includes at least onecomposite lead 597 ₁. For one embodiment, a majority of the leadscorresponding to the VCC power input pins are composite leads. Foranother embodiment, each VCC power input pin corresponds to at least twoVCC power input chip bond pads 466. For a further embodiment, the numberof VCC power input chip bond pads 466 is at least two times the numberof VCC power input pins of the memory package. For yet anotherembodiment, the number of VCC power input chip bond pads 466 is equal toor greater than three times the number of VCC power input pins of thememory package.

The composite leads 594 ₁ effectively allow use of a single VSS powerinput pin to provide the ground potential VSS to both sides 484 and 486of the memory chip 460 without routing a power connection through thesemiconductor die. The composite leads 597 ₁ effectively allow use of asingle VCC power input pin to provide the supply potential VCC to bothsides 484 and 486 of the memory chip 460 without routing a powerconnection through the semiconductor die. The composite leads 594 ₁ and597 ₁ thus act as another level of metalization on the die withoutimpacting on the die real estate. Furthermore, as the leads of the LOCleadframe 590 are generally much wider and thicker than a typicalsemiconductor die metalization layer, the IR drops across the die can begreatly reduced using the composite leads 594 ₁ and 597 ₁ in lieu of asemiconductor die metalization layer.

As depicted in FIG. 5, one composite lead 597 ₁ corresponding to pin #1of the memory package 150 originates in a corner of the leadframe 590 inthe fourth quadrant 558 and terminates in both the first quadrant 552and the fourth quadrant 558. One composite lead 594 ₁ corresponding topin #28, or number n+1, of the memory package 150 further originates inan opposite corner of the leadframe 590 in the second quadrant 554 andterminates in both the second quadrant 554 and the third quadrant 556.

As further depicted in FIG. 5, one composite lead 597 ₁ corresponding tocenter pin #14, or number (n+1)/2, of the memory package 150 originatesfrom the side 586 of the leadframe 590 and terminates in both the firstquadrant 552 and the third quadrant 556. One composite lead 5941corresponding to center pin #41, or number (3n+1)/2, of the memorypackage 150 further originates from the opposite side 584 of theleadframe 590, yet also terminates in both the first quadrant 552 andthe third quadrant 556.

For an embodiment such as that depicted in FIG. 5, three VCC power inputchip bond pads 466 are located near corners of the memory chip 460 forcoupling to pin #1 of the memory package 150; four VCC power input chipbond pads 466 are located near the center of a side of the memory chip460 (two power input chip bond pads on each side 484 and 486 of thememory chip 460) for coupling to pin #14 of the memory package 150; twoVCC power input chip bond pads 466 are located near a corner of thememory chip 460 for coupling to pin #27 of the memory package 150; threeVSS power input chip bond pads 468 are located near corners of thememory chip 460 for coupling to pin #28 of the memory package 150; fourVSS power input chip bond pads 468 are located near the center of a sideof the memory chip 460 (two power input chip bond pads on each side 484and 486 of the memory chip 460) for coupling to pin #41 of the memorypackage 150; and two VSS power input chip bond pads 468 are located neara corner of the memory chip 460 for coupling to pin #54 of the memorypackage 150. Providing supply potentials and ground potentials, such asVCC and VSS, to power input chip bond pads in corners and along thelength of the memory chip improves internal power distribution, reduceshot spots and decreases signal noise, thus improving device operationand device integrity. Additional improvements may be possible byproviding further additional power input chip bond pads.

Additional leads of the LOC leadframe 590 correspond to clock andcontrol signal pins as well as DQ power input pins as is apparent fromviewing FIG. 5 with reference to FIG. 3. Also shown in FIG. 5 is acomposite lead 598 corresponding to pin #40 of the memory package 150.Composite lead 598 facilitates coupling the control signal RP# to chipbond pads in multiple quadrants and on both sides of the memory chip460. Thus, the composite leads may correspond to interconnect pins otherthan power input pins.

As noted previously, memory devices are generally a component of anelectronic system. In such electronic systems, a processor is coupled tothe memory device, generally through the chip bond pads. Such couplingof a processor and a memory device may further include coupling theprocessor to the chip bond pads of a memory chip through theinterconnect pins of a memory package and leads of a leadframe asdescribed in accordance with the various embodiments of the invention.

CONCLUSION

Various embodiments of the invention have been shown for providingoperational advantages in semiconductor memory devices through chiparchitecture and package assembly. The various embodiments of theinvention include memory chips having a memory device coupled to firstpower input chip bond pads and second power input chip bond pads.Embodiments include at least one first power input chip bond pad locatedin each of at least three quadrants of the memory chip. Furtherembodiments include at least one second power input chip bond padlocated in each of at least three quadrants of the memory chip.Embodiments include memory chips in memory assemblies having chip bondpads on both sides of the memory chip shorted to each other by a singlelead of a lead-over-chip leadframe. Memory devices of variousembodiments contain banks of non-volatile flash memory cells and haveaccess commands synchronized to a system clock.

LOC leadframes may be used to couple the chip bond pads to theinterconnect pins of the memory package to produce an integrated circuitmemory assembly. LOC leadframes in accordance with the invention containat least one composite lead for coupling an interconnect pin to chipbond pads located in multiple quadrants or on opposite sides of thememory chip.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement that is calculated to achieve the same purpose maybe substituted for the specific embodiments shown. Many adaptations ofthe invention will be apparent to those of ordinary skill in the art.Accordingly, this application is intended to cover any adaptations orvariations of the invention. It is manifestly intended that thisinvention be limited only by the following claims and equivalentsthereof.

1. A memory assembly, comprising: a memory package having a plurality ofinterconnect pins, wherein the plurality of interconnect pins comprisesa plurality of first power input pins located on a first side of thememory package, the first power input pins independent of each other; alead-over-chip leadframe having a plurality of leads coupled to theplurality of interconnect pins in a one-to-one relationship; and amemory chip coupled to the plurality of leads, wherein the memory chipcomprises: a substrate having two sides and four quadrants; a memorydevice fabricated on the substrate between the two sides; and aplurality of first power input chip bond pads fabricated on thesubstrate and coupled to the memory device, wherein each first powerinput chip bond pad is further coupled to one of the plurality of firstpower input pins through one of the leads; wherein at least one of thefirst power input chip bond pads is located in each of at least three ofthe quadrants of the substrate; and wherein at least one of the firstpower input chip bond pads is located near a center of each of the twosides of the substrate.
 2. The memory assembly of claim 1, wherein theplurality of first power input pins is adapted to be coupled to a supplypotential.
 3. The memory assembly of claim 1, wherein the plurality offirst power input pins is adapted to be coupled to a ground potential.4. The memory assembly of claim 1, further comprising a plurality ofsecond power input pins located on a second side of the memory packageand coupled one-to-one to second power input chip bond pads fabricatedon the substrate and coupled to the memory device.
 5. The memoryassembly of claim 4, wherein each second power input chip bond pad isfurther coupled to one of the plurality of second power input pinsthrough one of the leads.
 6. The memory assembly of claim 5, wherein theplurality of first power input pins is adapted to be coupled to a groundpotential and the plurality of second power input pins is adapted to becoupled to a supply potential.
 7. A memory assembly, comprising: amemory package having a plurality of interconnect pins, wherein theplurality of interconnect pins comprises a plurality of first powerinput pins located on a first side of the memory package for coupling toa ground potential and a plurality of second power input pins located ona second side of the memory package for coupling to a supply potential,the first power input pins independent of each other and the secondpower input pins independent of each other; a lead-over-chip leadframehaving a plurality of leads coupled to the plurality of interconnectpins in a one-to-one relationship; and a memory chip coupled to theplurality of leads, wherein the memory chip comprises: a substratehaving four quadrants; a memory device fabricated on the substrate; aplurality of first power input chip bond pads for receiving the groundpotential, the plurality of first power input chip bond pads fabricatedon the substrate and coupled to the memory device; and a plurality ofsecond power input chip bond pads for receiving the supply potential,the plurality of second power input chip bond pads fabricated on thesubstrate and coupled to the memory device; wherein at least two leadsare each coupled to at least two first power input chip bond padslocated in multiple quadrants of the substrate; and wherein at least twoleads are each coupled to at least two second power input chip bond padslocated in multiple quadrants of the substrate.
 8. A memory assembly,comprising: a memory package having a plurality of interconnect pins; alead-over-chip leadframe having a plurality of leads coupled to theplurality of interconnect pins in a one-to-one relationship; and amemory chip coupled to the plurality of leads, wherein the memory chipcomprises: a substrate having a first side and a second side; a memorydevice fabricated on the substrate between the first and second sides;and a plurality of chip bond pads fabricated on the substrate andcoupled to the memory device; wherein a first chip bond pad locatedbetween the memory device and the first side of the substrate near acenter of the first side is shorted to a second chip bond pad locatedbetween the memory device and the second side of the substrate near acenter of the second side by one of the plurality of leads of theleadframe.
 9. A memory assembly, comprising: a memory package having aplurality of interconnect pins; a lead-over-chip leadframe having aplurality of leads coupled to the plurality of interconnect pins in aone-to-one relationship; and a memory chip coupled to the plurality ofleads, wherein the memory chip comprises: a substrate having fourquadrants and further having two sides parallel a major axis of thesubstrate; a memory device fabricated on the substrate; and a pluralityof first power input chip bond pads for receiving a first power input,the plurality of first power input chip bond pads fabricated on thesubstrate along each of the two sides and coupled to the memory device;a plurality of second power input chip bond pads for receiving a secondpower input, the plurality of second power input chip bond padsfabricated on the substrate along each of the two sides and coupled tothe memory device; wherein at least one of the first power input chipbond pads is located in each of at least three of the quadrants of thesubstrate; wherein at least one of the first power input chip bond padsis located near a center of each of the two sides; wherein at least oneof the second power input chip bond pads is located in each of at leastthree of the quadrants of the substrate; and wherein at least one of thesecond power input chip bond pads is located near a center of each ofthe two sides.
 10. The memory assembly of claim 9, wherein at least oneof the first power input chip bond pads is located in each of a first,second and third quadrants of the substrate and wherein at least one ofthe second power input chip bond pads is located in each of a first,third and fourth quadrants of the substrate.
 11. The memory chip ofclaim 9, wherein the first power input is a supply potential.
 12. Thememory chip of claim 9, wherein the first power input is a groundpotential.
 13. A memory assembly, comprising: a memory package having aplurality of interconnect pins; a lead-over-chip leadframe having aplurality of leads coupled to the plurality of interconnect pins in aone-to-one relationship; and a memory chip coupled to the plurality ofleads, wherein the memory chip comprises: a substrate having a firstside substantially parallel to a major axis of the memory chip andhaving two ends and a center, a second side substantially parallel tothe major axis and having two ends and a center, and four corners,wherein a corner is located at each end of the first and second sides; amemory device fabricated on the substrate; at least five first powerinput chip bond pads for coupling the memory device to a supplypotential, wherein at least one first power input chip bond pad islocated near each of three corners, at least one first power input chipbond pad is located near the center of the first side, and at least onefirst power input chip bond pad is located near the center of the secondside; and at least five second power input chip bond pads for couplingthe memory device to a ground potential, wherein at least one secondpower input chip bond pad is located near each of three corners, atleast one second power input chip bond pad is located near the center ofthe first side, and at least one second power input chip bond pad islocated near the center of the second side.
 14. The memory assembly ofclaim 13, wherein two first power input chip bond pads are located neara first corner, two first power input chip bond pads are located near athird corner, one first power input chip bond pad is located near afourth corner, two first power input chip bond pads are located near thecenter of the first side, and two first power input chip bond pads arelocated near the center of the second side; and wherein two second powerinput chip bond pads are located near the first corner, one second powerinput chip bond pad is located near a second corner, two second powerinput chip bond pads are located near the third corner, two second powerinput chip bond pads are located near the center of the first side, andtwo second power input chip bond pads are located near the center of thesecond side.
 15. A memory assembly, comprising: a memory package havinga plurality of interconnect pins; a lead-over-chip leadframe having aplurality of leads coupled to the plurality of interconnect pins in aone-to-one relationship; and a memory chip coupled to the plurality ofleads, wherein the memory chip comprises: a substrate having fourquadrants between two sides, the sides being parallel a major axis ofthe substrate; a memory device fabricated on the substrate; a pluralityof supply potential power input chip bond pads for receiving a supplypotential, the plurality of supply potential power input chip bond padsfabricated on the substrate along each of the two sides and coupled tothe memory device; and a plurality of ground potential power input chipbond pads for receiving a ground potential, the plurality of groundpotential power input chip bond pads fabricated on the substrate alongeach of the two sides and coupled to the memory device; wherein at leastone of the supply potential power input chip bond pads is located ineach of at least three of the quadrants of the substrate and near acenter of each of the two sides; and wherein at least one of the groundpotential power input chip bond pads is located in each of at leastthree of the quadrants of the substrate and near the center of each ofthe two sides.
 16. The memory assembly of claim 15, wherein at least oneof the supply potential power input chip bond pads is located in each ofa first, second and third quadrants of the substrate and wherein atleast one of the ground potential power input chip bond pads is locatedin each of the first and third quadrants of the substrate and a fourthquadrant of the substrate.
 17. A memory assembly, comprising: a memorypackage having a plurality of interconnect pins; a lead-over-chipleadframe having a plurality of leads coupled to the plurality ofinterconnect pins in a one-to-one relationship; and a memory chipcoupled to the plurality of leads, wherein the memory chip comprises: asubstrate having a first side substantially parallel to a major axis ofthe memory chip and having two ends and a center, a second sidesubstantially parallel to the major axis and having two ends and acenter, and four corners, wherein a corner is located at each end of thefirst and second sides; a memory device fabricated on the substrate; afirst supply potential power input chip bond pad located near a firstcorner; a second supply potential power input chip bond pad located nearthe center of the first side; a third supply potential power input chipbond pad located near a third corner; a fourth supply potential powerinput chip bond pad located near the center of the second side; a fifthsupply potential power input chip bond pad located near a fourth corner;a first ground potential power input chip bond pad located near thefirst corner; a second ground potential power input chip bond padlocated near the center of the first side; a third ground potentialpower input chip bond pad located near a second corner; a fourth groundpotential power input chip bond pad located near the third corner; and afifth ground potential power input chip bond pad located near the centerof the second side; wherein each power input chip bond pad is coupled tothe memory device.
 18. The memory assembly of claim 17, furthercomprising: a sixth supply potential power input chip bond pad locatednear the first corner; a seventh supply potential power input chip bondpad located near the center of the first side; an eighth supplypotential power input chip bond pad located near the third corner; and aninth supply potential power input chip bond pad located near the centerof the second side.
 19. The memory assembly of claim 17, furthercomprising: a sixth ground potential power input chip bond pad locatednear the first corner; a seventh ground potential power input chip bondpad located near the center of the first side; an eighth groundpotential power input chip bond pad located near the third corner; and aninth ground potential power input chip bond pad located near the centerof the second side.